Single Clock FIFO

Block Diagram

I2C Master



  • Configurable depth and data width
  • Full/Empty flags
  • FIFO fullness counter
  • Support for almost used and almost empty flags
  • Technology independent, can be synthesized to any FPGA, CPLD or ASIC vendor
  • Provided as VHDL source code
  • Includes 5 hours of email support