ARINC 429 Transmitter DO-254 IP Corepedro2021-03-05T14:54:39+01:00
ARINC 429 Transmitter DO-254 IP Core
The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
This “Mark 33 Digital Information Transfer System (DITS)” specification defines how to transfer digital data between avionics systems elements. The transmission is done over a twisted and shielded pair of wires and bi-directional data flow is not permitted. An extra twisted and shielded pair of wires is used when data is required to flow both ways.
The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
A radiation-hardened version with Triple Modular Redundancy (TMR) is also available.
Safe Core Devices provides two separate IP Cores, one for the ARINC 429 Rx IP Core and one for the ARINC 429 Tx IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.The ARINC 429 Tx IP Core is already being used in one program: a civil large airplane program, as DAL A.
ARINC 429 Transmitter Key Features:
Compliant to ARINC Specification 429-17 (May 17, 2004)
Design Assurance Level A according to DO-254 / ED-80
Single clock domain fully synchronous design
Configurable data rate
Multiple error checking (frequency, gap, parity and form)
Interfaces to standard line drivers without additional logic
Simple interface to user’s logic
TMR coding for radiation-hardening (optional)
Technology independent, can be synthesized to any FPGA / ASIC vendor.
The following tables show some examples of implementing the A429 Tx Core in different technologies and devices. Note that the A429 Tx Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).
Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.
No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multi-cycle, false paths, etc. defined).
The results are provided for an A429 Tx Core without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk’ frequency.