SDRAM Controller DO-254 IP Core

The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as specified in the JEDEC Standard No. 21-C Page Release 12.

Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes. SDRAM is still being manufactured and the maturity of this technology makes it ideal for systems that need performance at a low cost.

The SDRAM Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.

SDRAM Controller Block Diagram

SDRAM Controller Key Features:

  • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
  • Compliant to JEDEC Standard No. 21-C Page Release 12
  • Single clock domain fully synchronous design
  • Configurable to support any SDRAM device
  • Very low latency: the command is issued on the clock cycle following the request
  • Fully deterministic handshake interface that allows chaining of requests (read/write/terminate) to maximize bandwidth
  • Intelligent bank management to reduce ACTIVE and PRECHARGE operations to the minimum
  • Static configuration to provide best area and speed results for a given application
  • Automatic management of the initialization cycle
  • Automatic management of the refresh cycles
  • Issue of read/write commands with auto-precharge under user control (on a per command basis)
  • Supports all the burst termination possibilities described by the JEDEC
  • TMR coded for SEU immunity (optional)
  • Technology independent (can be synthesized to any FPGA/CPLD vendor)