SPI Master DO-254 IP Core
The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include Secure Digital cards and liquid crystal displays. SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.
The SPI Master IP Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Safe Core Devices provides two separate IP Cores, one for the SPI Master IP Core and one for the SPI Slave IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
SPI Master Key Features:
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual)
- Configurable data rate
- Configurable phase, polarity and word size
- Configurable number of slaves
- Single clock domain fully synchronous design
- Simple interface to user’s logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)