I2C Master Controller

Block Diagram

I2C Master



  • Technology independent, can be synthesized to any FPGA, CPLD or ASIC vendor
  • Provided as VHDL source code
  • Fully compliant to the Philips (now NXP) “I2C-bus specification and user manual”, Rev. 5 – 9 October 2012, for Standard-mode, Fast-mode and Fast-mode Plus (Fm+)
  • Configurable at standard data rates (100kHz, 400kHz or 1000kHz) or custom data-rates up to half the input frequency
  • Support for all Options: Multi-master, Synchronization, Arbitration, Clock stretching, 10-bit slave address, General Call address, Software Reset and START byte
  • Transmit and Receive functions simplified via FIFO interfaces
  • I2C Slave available separately
  • Includes 10 hours of email support