Restoring Division

Block Diagram

I2C Master



  • Technology independent, can be synthesized to any FPGA, CPLD or ASIC vendor
  • Provided as VHDL source code
  • Implements division using programmable logic (no hard blocks)
  • Full precision in signed fixed-point arithmetic
  • Configurable word size
  • Configurable number of fractional part increment
  • Includes 10 hours of email support