MIL-STD-1553C Remote Terminal DO-254 IP Core

The MIL_1553 RT IP Core implements a Remote Terminal as specified in the MIL-STD-1553C specification.

MIL-STD-1553C is the military specification defining a Digital Time Division Command/Response Multiplexed Data Bus operating at 1 Mbps. The 1553 databus is a dual-redundant, bidirectional, Manchester II encoded databus with a high bit error reliability. All bus communications are controlled and initiated by the bus controller. Remote terminal devices attached to the bus respond to controller commands.

The MIL_1553 RT IP Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.

MIL-STD-1553C Remote Terminal Key Features:

Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
Compliant to the MIL-STD-1553C, 28 February 2018
Configurable number of Buses: 1 or 2
Tested as specified in the AS4111 Rev. A (2017-08)
User configurable illegal commands
Interfaces to standard 1553 bus transceivers
Single Clock Domain, fully synchronous design
Simple interface to user’s logic
TMR coded for SEU immunity (optional)
Technology independent (can be synthesized to any FPGA/CPLD vendor)

Implementation Details

The following tables show some examples of implementing the MIL_1553 RT IP Core in different technologies and devices. Note that the MIL_1553 RT IP Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multicycle, false paths, etc. defined).

The results are provided for a MIL_1553 RT IP Core with:

Two (2) 1553 data buses
A 20 MHz input clock (50 ns period)
without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk’ frequency.

The MIL_1553 RT IP Core has been wrapped in a higher level that will serialize the received data. This adds a little bit of logic, but it its size can be considered negligible.

ACTEL / MICROSEMI

FPGA Type	*Maximum ‘clk‘ Frequency*	Logic Modules (CORE)
ProASIC3 (A3P1000 484FBGA I Std)	57 MHz	2067
IGLOO (AGL1000V5 484FBGA I Std)	47 MHz	2067
Fusion (AFS1500 676FBGA I Std)	57 MHz	2067
IGLOO2 (M2GL050T 484FBGA Std)	103 MHz	SEQUENTIAL: 920 LUTs: 740
Polarfire (MPF050T 484FCVG Std)	146 MHz	SEQUENTIAL: 920 LUTs: 735
RTG4 (RT4G150 CG1657 Std)	94 MHz	SEQUENTIAL: 920 LUTs: 739

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